[Lancelot] 1st post!
H. Peter Anvin
hpa at zytor.com
Thu Jan 29 16:56:59 PST 2004
Tommy Thorn wrote:
> Even this list is called Lancelot, I'll treat it as a general Nios Dev
> board list :-)
> Here are a few gotcha's from my latest experience, all of which doesn't
> show up with a :
> 0) Be careful with unassigned ports in the top-level module.
> I used to export a bunch of ports for my Icarus Verilog simulation.
> However, if I forgot to remove them before synthesis my design would
> spontaneously reset and load the safe design (the web server)!
> Clearly, some of the pins on the EP1C20 doesn't like to be frobbed.
I think there is actually an output pin to "load safe"; you can also
write a config from the EP1C20 so...
> 1) Missing an "else" in an
> if (...) begin ...
> end else if (....) begin
> chain will not make the compiler complain and most likely means
Same happens under C :)
> 2) Asynchronous latches, like
> always @*
> if (foo) bar <= 1;
> are prone to glitches (did _not_ show up under Icarus).
Yeah, I think it's a good methodology to only use clock-driven elements.
> There were actually very few bugs in my design, but they were hard to
> find, especially because everything worked fine under Icarus. I still
> recommend using Icarus as the turn-around time is *MUCH* shorter, it runs
> under Linux, and is much easier to instrument. But clearly, the closer
> the simulated design is to the Real Thing, the better.
Where can one get Icarus? Sounds really interesting...
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