[Lancelot] New version of ABC80-in-FPGA

[H. Peter Anvin]

[För svensktalande, ursäkta engelskan...]

I have released a new version (16) of my ABC80 in an FPGA.  The big 
difference versus the previous version is that this one models the ABC80 
sound generator.

     ftp://ftp.zytor.com/pub/fpga/abc80/abc80-16.tar.bz2
     ftp://ftp.zytor.com/pub/fpga/abc80/abc80-16.zip

Complete list of changes:

Changes in release 16:
----------------------
* Support the ABC80 sound generator.  The original ABC80 had an
   SN76477 semianalog synthesizer chip, largely crippled by using fixed
   RC circuits for its adjustables.  For the FPGA, emulate the operation
   using digital logic, but I believe the correspondance should be very
   good, at least to the extent that the real SN76477 matches the
   datasheet.  There is clearly *some* differences, or "out 6,255"
   would be silent on ABC80.  I simply made a guess as to how those
   sounds should be generated.  If someone with a real ABC80 could
   record a set of files of all 128 sounds I might be able to get even
   closer.

   1 REM This program plays all 128 sounds in order
   2 FOR I%=1% to 255% STEP 2%
   3 GET Z$
   4 PRINT I%
   5 OUT 6%,0%,6%,I%
   6 NEXT I%
   7 GET Z$
   8 OUT 6%,0%

* The display now shows the frequency in MHz by default.

* The LEDs can now be controlled programmatically if desired.

   OUT 148,X    X = 1 to control single LEDs + 2 to control display
   OUT 149,L    Sets the individual LEDs
   OUT 150,A    Sets the right display (units)
   OUT 151,B    Sets the left display (tens)

   All of these can be read back via INP(port), too.

* Centralize all the non-ABC-compatible register handling (MMU, turbo,
   LEDs.)  The turbo can now be read back (via INP(144)), in addition
   to the MMU registers which have always been readable.

* For those sick enough to want it, the cassette port is now connected
   to the following pins on Prototype Connector 1 (J11):

   Relay   - pin 29
   Output  - pin 28
   Input   - pin 38
   Ground  - pin 26, 30 and 40

   These signals are 5V and TTL-compatible.  +5V is available on pin 2
   of J12.  See page 20 of the "Nios Development Board Reference
   Manual, Cyclone Edition" (version 1.0).