[Lancelot] VGA clk

Wei Mark Fang gjf01 at yahoo.com
Fri Feb 4 15:55:11 PST 2005

I'm asking about the VGA clk because I am working on a
design (on the Stratix Professional Board) that
utilizes the on-board SDRAM and the Lancelot DAC I
attached on. Currently, the design is configured at
50Mhz. The SDRAM (U57) must be at the same frequency
as the core, so I drive it using a pll. 

I need the SDRAM at the core frequency of 50Mhz, but
since I want 640x480 resolution, I have to get a 25Mhz
clk signal to the DAC. However, since the DAC and the
SDRAM use the same clock buffer (U2, ie. PIN_E15),
this is impossible to do. The problem is that it seems
I can only distribute a single clock to various parts
of the board (external units). 

The only solution I see right now is to lower the core
frequency to 25Mhz, to match the required frequency of
DAC for generating 640x480 resolution. But this is not
what I want to do. Do you see other solutions?

Thanks for your insights.


 --- "H. Peter Anvin" <hpa at zytor.com> wrote: 
> Tommy Thorn wrote:
> > 
> > Well, 25MHz maps nicely to 680x480 VESA mode.  I
> don't know of any modes using
> > 50MHz.   Finially, is the DAC even rated that
> high?  Why do you care?  You can
> > just use the DCM to devide it down.
> > 
> If I remember right, the DAC is rated at 80 MHz,
> which is enough for 
> 1024x768.
> Ultimately the clock frequency you need is a result
> of the resolution 
> you want.
> 	-hpa
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