[Lancelot] VGA clk
Wei Mark Fang
gjf01 at yahoo.com
Mon Feb 14 19:16:38 PST 2005
I tried using 25Mhz for the FSM that generates the
timing signals, and set the clk of the DAC at 50Mhz
(same as SDRAM). The result is not good. I programmed
it to display 2 columns of different colors. However,
it showed zig-zags of the 2 colors, all misaligned.
I thought about the fact that the DAC is at twice the
freq as the timing FSM. Doesn't each line appear
stretched out? I mean the DAC is clocking each pixel
twice, so the scanner will refresh 2 pixels with the
same value. How must the timing FSM be adjusted to
account for that? I am quite unsure, as I don't have a
very good grasp of how VGA monitors work.
Thanks for your help.
-Mark
--- Marco <marco at fpga.nl> wrote:
> Hi Mark,
>
> This was one of my comments when I saw the Stratix
> Nios board schematics.
> The SDRAM and both expansion boards must run at the
> same frequency, while
> the Stratix device has some many PLLs. Unfortunately
> the board layout had
> already finished, but Altera used my recommendation
> for the Cyclone board;
> the SDRAM is feed by another PLL than the expansion
> boards.
>
> To solve your problem you can 'over clock' the video
> DAC. Like hpa says the
> maximum frequency of the video DAC is 80 MHz. Feed
> the SDRAM and Lancelot
> board with the 50 MHz clock and connect the internal
> Lancelot video clock to
> 25 Mhz. Now the video DAC clocks in double pixels,
> but the video controller
> is still responsible video timing, so effectively
> you get an 640 x 480
> picture.
>
> Yesterday I posted a new version of the Lancelot
> controller. It supports the
> (undocumented) Avalon lock signal, which forces the
> memory to be locked to
> Lancelot while new video data is fetched. This
> solves the issue when Nios
> and Lancelot are using the same memory and Lancelot
> can't read a new video
> line on time. You can download the Lancelot
> reference design at my website
> (http://www.fpga.nl)
>
> Best Regards,
>
> Marco
> www.FPGA.nl
>
> -----Original Message-----
> From: lancelot-bounces at zytor.com
> [mailto:lancelot-bounces at zytor.com] On
> Behalf Of Wei Mark Fang
> Sent: zaterdag 5 februari 2005 0:55
> To: H. Peter Anvin; Tommy Thorn
> Cc: lancelot at zytor.com
> Subject: Re: [Lancelot] VGA clk
>
> I'm asking about the VGA clk because I am working on
> a design (on the
> Stratix Professional Board) that utilizes the
> on-board SDRAM and the
> Lancelot DAC I attached on. Currently, the design is
> configured at 50Mhz.
> The SDRAM (U57) must be at the same frequency as the
> core, so I drive it
> using a pll.
>
> I need the SDRAM at the core frequency of 50Mhz, but
> since I want 640x480
> resolution, I have to get a 25Mhz clk signal to the
> DAC. However, since the
> DAC and the SDRAM use the same clock buffer (U2, ie.
> PIN_E15), this is
> impossible to do. The problem is that it seems I can
> only distribute a
> single clock to various parts of the board (external
> units).
>
> The only solution I see right now is to lower the
> core frequency to 25Mhz,
> to match the required frequency of DAC for
> generating 640x480 resolution.
> But this is not what I want to do. Do you see other
> solutions?
>
> Thanks for your insights.
>
> -Mark
>
> --- "H. Peter Anvin" <hpa at zytor.com> wrote:
> > Tommy Thorn wrote:
> > >
> > > Well, 25MHz maps nicely to 680x480 VESA mode. I
> > don't know of any modes using
> > > 50MHz. Finially, is the DAC even rated that
> > high? Why do you care? You can
> > > just use the DCM to devide it down.
> > >
> >
> > If I remember right, the DAC is rated at 80 MHz,
> which is enough for
> > 1024x768.
> >
> > Ultimately the clock frequency you need is a
> result of the resolution
> > you want.
> >
> > -hpa
> >
> > _______________________________________________
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> >
>
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