[Lancelot] Slow lower order byte on fse_d?

Tommy Thorn tommy at numba-tu.com
Tue Jul 26 18:13:20 PDT 2005

I've spent quite some time now, trying to understand why I couldn't run 
the SRAM as fast as I expected and have reached the unavoidable 
conclusion that the lower order byte on fse_d is slower then the rest (= 
has a higher captive load?).  Incidently, the only thing that's 
different about this byte is that it's connected to the AMD flash ram 
also, unlike the other bytes.

It would be nice to know if anyone else have seen this.

I have a little test design to illustrate (below).  When run with 
WITH_READ_WAIT=1 it succeeds (all leds lit), WITH_READ_WAIT=0 it fails 
and from the debugging output we find that it saw ..ca8601 instead of 
the expected ..ca8643  Note, this is with a 50Mhz, so we are well within 
the 10ns for the fastest read cycle.

I've run many experiments, and they all agree, only the lower byte lag 
behind.  AFAICT, I've correctly disabled the flash RAM and the Ethernet. 
  I'm at a loss.


`timescale 1ns/10ps
module tester(input wire clk20ns,  // 50MHz - 20ns period
               input wire reset_n,

               output reg  [17:0] sram_a,
               inout  wire [31:0] sram_d,
               output reg         sram_cs_n,
               output reg   [3:0] sram_be_n,
               output reg         sram_oe_n,
               output reg         sram_we_n,
               output reg  [31:0] debug);

    reg [31:0]        sram_d_out    = 32'd0;
    reg               sram_d_out_en = 1'b0;
    assign            sram_d        = sram_d_out_en ? sram_d_out : 

    parameter   N = 3*4;
    parameter   SEED = 33'h87654321;
    parameter   WITH_READ_WAIT = 0;  // Flip this to insert a wait state 
for reading.

    parameter   S_START        = 4'd0;
    parameter   S_PRE_WRITE    = 4'd1;
    parameter   S_WRITING      = 4'd2;
    parameter   S_WROTE        = 4'd3;
    parameter   S_READ         = 4'd4;
    parameter   S_SUCCEED      = 4'd5;
    parameter   S_FAILED       = 4'd6;
    parameter   S_READ_WAIT    = 4'd7; // Wait state for reading

    reg  [ 3:0] state = S_START;

    reg [17:0]  addr;
    reg  [32:0] lfsr;
    wire [32:0] lfsr_next = {lfsr[31:0], ~lfsr[32] ^ lfsr[19]};

    reg  [31:0] data_latched, data_expected;

    always @(posedge clk20ns) if (reset_n)
      state <= S_START;
    else case (state)
            S_START: begin
               sram_d_out_en    <= 1'b1;
               sram_oe_n        <= 1'b1;
               sram_cs_n        <= 1'b0; // Select SRAM
               sram_be_n        <= 4'b0;

               data_latched     <= 0;
               data_expected    <= 0;
               lfsr             <= SEED;
               addr             <= 18'd0;

               state            <= S_WROTE;

            /* Writing the SRAM. */

            S_PRE_WRITE: begin                  /* This phase presents 
the data. */
               sram_we_n        <= 1'b0;        /* Only transition 
allowed is we. */
               state            <= S_WRITING;
            S_WRITING: begin                    /* This phase writes the 
data. */
               sram_we_n        <= 1'b1;        /* Only transition 
allowed is we. */
               state            <= S_WROTE;
            S_WROTE: begin                      /* This phase holds the 
data. */
               if (addr != N) begin
                  sram_a        <= addr;
                  sram_d_out    <= lfsr[31:0];

                  addr          <= addr + 18'd1;
                  lfsr          <= lfsr_next;

                  state         <= S_PRE_WRITE;
               end else begin
                  sram_a        <= 18'd0;
                  sram_oe_n     <= 1'b0;
                  sram_d_out_en <= 1'b0;
                  sram_d_out    <= 32'h0;

                  addr	       <= 18'd1;
                  lfsr          <= SEED;

//                 state         <= WITH_READ_WAIT ? S_READ_WAIT : S_READ;
                  state         <= S_READ_WAIT;

            /* Verifying the SRAM. */

            S_READ_WAIT: begin
                  state         <= S_READ;
            S_READ: begin
               if (data_latched != data_expected)
                 state          <= S_FAILED;
               else if (sram_a == N)
                 state          <= S_SUCCEED;
               else begin
                  sram_a        <= addr;
                  data_latched  <= sram_d;
                  data_expected <= lfsr[31:0];

                  addr          <= addr + 18'd1;
                  lfsr          <= lfsr_next;

                  state         <= WITH_READ_WAIT ? S_READ_WAIT : S_READ;
            S_SUCCEED: begin
               debug            <= ~0;
               $display("Test passed!");
            S_FAILED: begin
               debug           <= data_latched;
               $display("Failed at address %x: got %x, but expected %x",
                        sram_a, sram_d, lfsr);

module main();
    reg clk = 1;
    reg reset_n = 1;

    always #5 clk = ~clk;

    wire [31:0] sram_d;
    wire [17:0] sram_a;
    wire [ 3:0] sram_be_n;
    wire        sram_we_n,
    wire [31:0] debug;

    tester tester(clk, reset_n,
                  sram_a, sram_d, sram_cs_n, sram_be_n, sram_oe_n, 

    idt71v416s10 u35(sram_d[15: 0] , sram_a,
                     sram_we_n, sram_oe_n, sram_cs_n,
                     sram_be_n[0], sram_be_n[1]); // Yep, strange order...

    idt71v416s10 u36(sram_d[31:16], sram_a,
                     sram_we_n, sram_oe_n, sram_cs_n,
                     sram_be_n[2], sram_be_n[3]);
    initial begin
       $monitor($time, " %x %x", sram_a, sram_d);
       #321 reset_n = 0;
module main(input  wire         clkin,
             input  wire         reset_n,

             // Flash-SRAM-Ethernet bus
             output wire         flash_cs_n,   // Flash ROM CS#
             output wire         flash_oe_n,

             output wire  [22:0] fse_a,
             inout  wire  [31:0] fse_d,
             output wire         sram_cs_n,
             output wire   [3:0] sram_be_n,
             output wire         sram_oe_n,
             output wire         sram_we_n,
             output wire   [7:0] led,
             output wire   [7:0] s7_0,
             output wire   [7:0] s7_1,

             output wire         enet_aen,    // Ethernet Access Enable
             output wire   [3:0] enet_be_n    // Ethernet byte enables

    reg  [31:0]      counter;
    wire             my_reset     = counter == 0;

    wire [31:0]      debug;
    assign           led          = my_reset ? debug[23:16] : 8'hF0;
    assign           {s7_1,s7_0}  = ~debug[15:0];
    assign           fse_a[1:0]   = 2'd0;
    assign           fse_a[22:20] = 3'd0;

    assign           flash_cs_n   = 1'b1;
    assign           flash_oe_n   = 1'b1;
    assign           enet_aen     = 1'b1;
    assign           enet_be_n    = 4'b1111;

    always @(posedge clkin) begin
       if (~reset_n)
         counter <= 100000000;
       else if (counter)
         counter <= counter - 1;

    tester tester(clkin, ~my_reset,
                  fse_a[19:2], fse_d, sram_cs_n, sram_be_n, sram_oe_n, 
       0000          0000
      5    1        5    1
      5    1        5    1
       6666          6666
      4    2        4    2
      4    2        4    2
       3333   77     3333   77

       s7_1          s7_0


-------------- next part --------------
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.

# The default values for assignments are stored in the file
#		tester_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.

# Project-Wide Assignments
# ========================
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.0 SP0.21"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:04:59  JULY 26, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP0.21"
set_global_assignment -name VERILOG_FILE test2.v

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_W9 -to audio_l
set_location_assignment PIN_U10 -to audio_r
set_location_assignment PIN_H17 -to cf_a[0]
set_location_assignment PIN_J15 -to cf_a[10]
set_location_assignment PIN_H18 -to cf_a[1]
set_location_assignment PIN_H19 -to cf_a[2]
set_location_assignment PIN_W18 -to cf_a[3]
set_location_assignment PIN_K15 -to cf_a[4]
set_location_assignment PIN_J18 -to cf_a[5]
set_location_assignment PIN_J17 -to cf_a[6]
set_location_assignment PIN_J14 -to cf_a[7]
set_location_assignment PIN_H14 -to cf_a[8]
set_location_assignment PIN_J20 -to cf_a[9]
set_location_assignment PIN_J19 -to cf_bvd1
set_location_assignment PIN_J16 -to cf_bvd2
set_location_assignment PIN_B13 -to cf_cd1_n
set_location_assignment PIN_H20 -to cf_ce1_n
set_location_assignment PIN_U19 -to cf_ce2_n
set_location_assignment PIN_F20 -to cf_d[0]
set_location_assignment PIN_D20 -to cf_d[10]
set_location_assignment PIN_F17 -to cf_d[11]
set_location_assignment PIN_E18 -to cf_d[12]
set_location_assignment PIN_F16 -to cf_d[13]
set_location_assignment PIN_F19 -to cf_d[14]
set_location_assignment PIN_G16 -to cf_d[15]
set_location_assignment PIN_F15 -to cf_d[1]
set_location_assignment PIN_E19 -to cf_d[2]
set_location_assignment PIN_F18 -to cf_d[3]
set_location_assignment PIN_E17 -to cf_d[4]
set_location_assignment PIN_D17 -to cf_d[5]
set_location_assignment PIN_D18 -to cf_d[6]
set_location_assignment PIN_C18 -to cf_d[7]
set_location_assignment PIN_C19 -to cf_d[8]
set_location_assignment PIN_D19 -to cf_d[9]
set_location_assignment PIN_V19 -to cf_inpack_n
set_location_assignment PIN_G19 -to cf_iord_n
set_location_assignment PIN_G20 -to cf_iowr_n
set_location_assignment PIN_D13 -to cf_oe_n
set_location_assignment PIN_G17 -to cf_rdy
set_location_assignment PIN_U20 -to cf_reg_n
set_location_assignment PIN_G14 -to cf_wait_n
set_location_assignment PIN_V18 -to cf_we_n
set_location_assignment PIN_H16 -to cf_wp
set_location_assignment PIN_K5 -to clkin
set_location_assignment PIN_A14 -to enet_ads_n
set_location_assignment PIN_B15 -to enet_aen
set_location_assignment PIN_C16 -to enet_be_n[0]
set_location_assignment PIN_B16 -to enet_be_n[1]
set_location_assignment PIN_D16 -to enet_be_n[2]
set_location_assignment PIN_E16 -to enet_be_n[3]
set_location_assignment PIN_B17 -to enet_cycle_n
set_location_assignment PIN_C15 -to enet_datacs_n
set_location_assignment PIN_D15 -to enet_intrq0
set_location_assignment PIN_F14 -to enet_iochrdy
set_location_assignment PIN_A15 -to enet_ior_n
set_location_assignment PIN_E15 -to enet_iow_n
set_location_assignment PIN_C17 -to enet_lclk
set_location_assignment PIN_D3 -to enet_ldev_n
set_location_assignment PIN_B18 -to enet_rdyrtn_n
set_location_assignment PIN_A17 -to enet_w_r_n
set_location_assignment PIN_A12 -to flash_cs_n
set_location_assignment PIN_B12 -to flash_oe_n
set_location_assignment PIN_D12 -to flash_rw_n
set_location_assignment PIN_C12 -to flash_ry_by_n
set_location_assignment PIN_B4 -to fse_a[0]
set_location_assignment PIN_E4 -to fse_a[10]
set_location_assignment PIN_E5 -to fse_a[11]
set_location_assignment PIN_F3 -to fse_a[12]
set_location_assignment PIN_E3 -to fse_a[13]
set_location_assignment PIN_E2 -to fse_a[14]
set_location_assignment PIN_F4 -to fse_a[15]
set_location_assignment PIN_F5 -to fse_a[16]
set_location_assignment PIN_F2 -to fse_a[17]
set_location_assignment PIN_F1 -to fse_a[18]
set_location_assignment PIN_F6 -to fse_a[19]
set_location_assignment PIN_A4 -to fse_a[1]
set_location_assignment PIN_G5 -to fse_a[20]
set_location_assignment PIN_G1 -to fse_a[21]
set_location_assignment PIN_G2 -to fse_a[22]
set_location_assignment PIN_D5 -to fse_a[2]
set_location_assignment PIN_D6 -to fse_a[3]
set_location_assignment PIN_C5 -to fse_a[4]
set_location_assignment PIN_B5 -to fse_a[5]
set_location_assignment PIN_C2 -to fse_a[6]
set_location_assignment PIN_D2 -to fse_a[7]
set_location_assignment PIN_D4 -to fse_a[8]
set_location_assignment PIN_D1 -to fse_a[9]
set_location_assignment PIN_C6 -to fse_d[0]
set_location_assignment PIN_F8 -to fse_d[10]
set_location_assignment PIN_E8 -to fse_d[11]
set_location_assignment PIN_B8 -to fse_d[12]
set_location_assignment PIN_A8 -to fse_d[13]
set_location_assignment PIN_D8 -to fse_d[14]
set_location_assignment PIN_C8 -to fse_d[15]
set_location_assignment PIN_B9 -to fse_d[16]
set_location_assignment PIN_A9 -to fse_d[17]
set_location_assignment PIN_D9 -to fse_d[18]
set_location_assignment PIN_C9 -to fse_d[19]
set_location_assignment PIN_E6 -to fse_d[1]
set_location_assignment PIN_E9 -to fse_d[20]
set_location_assignment PIN_E10 -to fse_d[21]
set_location_assignment PIN_B10 -to fse_d[22]
set_location_assignment PIN_A10 -to fse_d[23]
set_location_assignment PIN_F10 -to fse_d[24]
set_location_assignment PIN_C10 -to fse_d[25]
set_location_assignment PIN_D10 -to fse_d[26]
set_location_assignment PIN_C11 -to fse_d[27]
set_location_assignment PIN_D11 -to fse_d[28]
set_location_assignment PIN_B11 -to fse_d[29]
set_location_assignment PIN_B6 -to fse_d[2]
set_location_assignment PIN_A11 -to fse_d[30]
set_location_assignment PIN_E11 -to fse_d[31]
set_location_assignment PIN_A6 -to fse_d[3]
set_location_assignment PIN_F7 -to fse_d[4]
set_location_assignment PIN_E7 -to fse_d[5]
set_location_assignment PIN_B7 -to fse_d[6]
set_location_assignment PIN_A7 -to fse_d[7]
set_location_assignment PIN_D7 -to fse_d[8]
set_location_assignment PIN_C7 -to fse_d[9]
set_location_assignment PIN_E14 -to led[0]
set_location_assignment PIN_E13 -to led[1]
set_location_assignment PIN_C14 -to led[2]
set_location_assignment PIN_D14 -to led[3]
set_location_assignment PIN_E12 -to led[4]
set_location_assignment PIN_F12 -to led[5]
set_location_assignment PIN_B3 -to led[6]
set_location_assignment PIN_B14 -to led[7]
set_location_assignment PIN_G15 -to p1_a21
set_location_assignment PIN_H15 -to p1_a28
set_location_assignment PIN_G18 -to p1_a29
set_location_assignment PIN_U18 -to p1_a38
set_location_assignment PIN_P27 -to p1_clkout
set_location_assignment PIN_L14 -to pld_clkfb
set_location_assignment PIN_L8 -to pld_clkout
set_location_assignment PIN_K6 -to proto1_clkout
set_location_assignment PIN_K14 -to proto2_clkout
set_location_assignment PIN_Y10 -to ps2_kclk
set_location_assignment PIN_V10 -to ps2_kdata
set_location_assignment PIN_T10 -to ps2_mclk
set_location_assignment PIN_Y9 -to ps2_mdata
set_location_assignment PIN_W10 -to ps2_sel
set_location_assignment PIN_C4 -to reset_n
set_location_assignment PIN_U6 -to s7_0[0]
set_location_assignment PIN_V6 -to s7_0[1]
set_location_assignment PIN_W7 -to s7_0[2]
set_location_assignment PIN_Y7 -to s7_0[3]
set_location_assignment PIN_R7 -to s7_0[4]
set_location_assignment PIN_T8 -to s7_0[5]
set_location_assignment PIN_V7 -to s7_0[6]
set_location_assignment PIN_U7 -to s7_0[7]
set_location_assignment PIN_T5 -to s7_1[0]
set_location_assignment PIN_U5 -to s7_1[1]
set_location_assignment PIN_V5 -to s7_1[2]
set_location_assignment PIN_W5 -to s7_1[3]
set_location_assignment PIN_T6 -to s7_1[4]
set_location_assignment PIN_T7 -to s7_1[5]
set_location_assignment PIN_W6 -to s7_1[6]
set_location_assignment PIN_Y6 -to s7_1[7]
set_location_assignment PIN_M2 -to sd_a[0]
set_location_assignment PIN_H6 -to sd_a[10]
set_location_assignment PIN_H5 -to sd_a[11]
set_location_assignment PIN_M1 -to sd_a[1]
set_location_assignment PIN_M6 -to sd_a[2]
set_location_assignment PIN_M4 -to sd_a[3]
set_location_assignment PIN_J8 -to sd_a[4]
set_location_assignment PIN_J7 -to sd_a[5]
set_location_assignment PIN_J6 -to sd_a[6]
set_location_assignment PIN_J5 -to sd_a[7]
set_location_assignment PIN_J4 -to sd_a[8]
set_location_assignment PIN_J3 -to sd_a[9]
set_location_assignment PIN_H7 -to sd_ba[0]
set_location_assignment PIN_H1 -to sd_ba[1]
set_location_assignment PIN_G3 -to sd_cas_n
set_location_assignment PIN_G7 -to sd_cke
set_location_assignment PIN_L13 -to sd_clk
set_location_assignment PIN_G6 -to sd_cs_n
set_location_assignment PIN_M5 -to sd_dq[0]
set_location_assignment PIN_P7 -to sd_dq[10]
set_location_assignment PIN_P2 -to sd_dq[11]
set_location_assignment PIN_P1 -to sd_dq[12]
set_location_assignment PIN_P6 -to sd_dq[13]
set_location_assignment PIN_P5 -to sd_dq[14]
set_location_assignment PIN_P3 -to sd_dq[15]
set_location_assignment PIN_P4 -to sd_dq[16]
set_location_assignment PIN_R1 -to sd_dq[17]
set_location_assignment PIN_R2 -to sd_dq[18]
set_location_assignment PIN_R6 -to sd_dq[19]
set_location_assignment PIN_M3 -to sd_dq[1]
set_location_assignment PIN_R5 -to sd_dq[20]
set_location_assignment PIN_R3 -to sd_dq[21]
set_location_assignment PIN_R4 -to sd_dq[22]
set_location_assignment PIN_T4 -to sd_dq[23]
set_location_assignment PIN_T2 -to sd_dq[24]
set_location_assignment PIN_T3 -to sd_dq[25]
set_location_assignment PIN_U1 -to sd_dq[26]
set_location_assignment PIN_U4 -to sd_dq[27]
set_location_assignment PIN_U2 -to sd_dq[28]
set_location_assignment PIN_U3 -to sd_dq[29]
set_location_assignment PIN_M7 -to sd_dq[2]
set_location_assignment PIN_V3 -to sd_dq[30]
set_location_assignment PIN_V2 -to sd_dq[31]
set_location_assignment PIN_N6 -to sd_dq[3]
set_location_assignment PIN_N1 -to sd_dq[4]
set_location_assignment PIN_N2 -to sd_dq[5]
set_location_assignment PIN_N4 -to sd_dq[6]
set_location_assignment PIN_N3 -to sd_dq[7]
set_location_assignment PIN_N5 -to sd_dq[8]
set_location_assignment PIN_N7 -to sd_dq[9]
set_location_assignment PIN_J2 -to sd_dqm[0]
set_location_assignment PIN_J1 -to sd_dqm[1]
set_location_assignment PIN_H4 -to sd_dqm[2]
set_location_assignment PIN_H3 -to sd_dqm[3]
set_location_assignment PIN_H2 -to sd_ras_n
set_location_assignment PIN_G4 -to sd_we_n
set_location_assignment PIN_V17 -to sram_be_n[0]
set_location_assignment PIN_V16 -to sram_be_n[1]
set_location_assignment PIN_W16 -to sram_be_n[2]
set_location_assignment PIN_T16 -to sram_be_n[3]
set_location_assignment PIN_W17 -to sram_cs_n
set_location_assignment PIN_Y17 -to sram_oe_n
set_location_assignment PIN_U16 -to sram_we_n
set_location_assignment PIN_W3 -to sw[0]
set_location_assignment PIN_Y4 -to sw[1]
set_location_assignment PIN_V4 -to sw[2]
set_location_assignment PIN_W4 -to sw[3]
set_location_assignment PIN_J13 -to ttya_cts
set_location_assignment PIN_M16 -to ttya_dcd
set_location_assignment PIN_M20 -to ttya_dsr
set_location_assignment PIN_M15 -to ttya_dtr
set_location_assignment PIN_M19 -to ttya_ri
set_location_assignment PIN_K19 -to ttya_rts
set_location_assignment PIN_K16 -to ttya_rxd
set_location_assignment PIN_M14 -to ttya_txd
set_location_assignment PIN_C13 -to ttyb_rxd
set_location_assignment PIN_A13 -to ttyb_txd
set_location_assignment PIN_T12 -to vga_b[0]
set_location_assignment PIN_T11 -to vga_b[1]
set_location_assignment PIN_W12 -to vga_b[2]
set_location_assignment PIN_W8 -to vga_b[3]
set_location_assignment PIN_Y12 -to vga_b[4]
set_location_assignment PIN_Y8 -to vga_b[5]
set_location_assignment PIN_V9 -to vga_b[6]
set_location_assignment PIN_U9 -to vga_b[7]
set_location_assignment PIN_R14 -to vga_blank_n
set_location_assignment PIN_T15 -to vga_g[0]
set_location_assignment PIN_W15 -to vga_g[1]
set_location_assignment PIN_Y15 -to vga_g[2]
set_location_assignment PIN_U15 -to vga_g[3]
set_location_assignment PIN_V15 -to vga_g[4]
set_location_assignment PIN_V14 -to vga_g[5]
set_location_assignment PIN_U14 -to vga_g[6]
set_location_assignment PIN_Y14 -to vga_g[7]
set_location_assignment PIN_T9 -to vga_hs
set_location_assignment PIN_V11 -to vga_m1
set_location_assignment PIN_U11 -to vga_m2
set_location_assignment PIN_U12 -to vga_r[0]
set_location_assignment PIN_V12 -to vga_r[1]
set_location_assignment PIN_T13 -to vga_r[2]
set_location_assignment PIN_R13 -to vga_r[3]
set_location_assignment PIN_Y13 -to vga_r[4]
set_location_assignment PIN_W13 -to vga_r[5]
set_location_assignment PIN_U13 -to vga_r[6]
set_location_assignment PIN_V13 -to vga_r[7]
set_location_assignment PIN_T14 -to vga_sync_n
set_location_assignment PIN_W14 -to vga_sync_t
set_location_assignment PIN_R9 -to vga_vs

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name TOP_LEVEL_ENTITY main

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C20F400C7
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Assembler Assignments
# =====================
set_global_assignment -name AUTO_RESTART_CONFIGURATION ON

# Design Assistant Assignments
# ============================
set_global_assignment -name ENABLE_DRC_SETTINGS ON

More information about the Lancelot mailing list