[Lancelot] 1st post!

[Tommy Thorn]

Even this list is called Lancelot, I'll treat it as a general Nios Dev
board list :-)

Here are a few gotcha's from my latest experience, all of which doesn't
show up with a :

0) Be careful with unassigned ports in the top-level module.
   I used to export a bunch of ports for my Icarus Verilog simulation.
   However, if I forgot to remove them before synthesis my design would
   spontaneously reset and load the safe design (the web server)!
   Clearly, some of the pins on the EP1C20 doesn't like to be frobbed.

1) Missing an "else" in an

     if (...) begin ...
     end else if (....) begin

   chain will not make the compiler complain and most likely means
   non-intended.

2) Asynchronous latches, like

   always @*
     if (foo) bar <= 1;

   are prone to glitches (did _not_ show up under Icarus).

3) Any minor divergence in the Verilog used for simulation is prone to hide
   bugs.

   Example: I hacked up a quick-and-dirty model of the Altera
   altsyncram but didn't bother to implement byte enables as I didn't use
   them.  I had forgotten about that it instantiation time, so the byte
   enables weren't hooked up and thus all writes were dropped on the floor.

   It's an unfortunate side effect of the flexibility of Verilog that the
   compiler doesn't catch a bunch of obvious mistakes.

There were actually very few bugs in my design, but they were hard to
find, especially because everything worked fine under Icarus.  I still
recommend using Icarus as the turn-around time is *MUCH* shorter, it runs
under Linux, and is much easier to instrument.  But clearly, the closer
the simulated design is to the Real Thing, the better.

/Tommy