[Lancelot] Slow lower order byte on fse_d?

[H. Peter Anvin]

Tommy Thorn wrote:
> I've spent quite some time now, trying to understand why I couldn't run 
> the SRAM as fast as I expected and have reached the unavoidable 
> conclusion that the lower order byte on fse_d is slower then the rest (= 
> has a higher captive load?).  Incidently, the only thing that's 
> different about this byte is that it's connected to the AMD flash ram 
> also, unlike the other bytes.
> 
> It would be nice to know if anyone else have seen this.
> 
> I have a little test design to illustrate (below).  When run with 
> WITH_READ_WAIT=1 it succeeds (all leds lit), WITH_READ_WAIT=0 it fails 
> and from the debugging output we find that it saw ..ca8601 instead of 
> the expected ..ca8643  Note, this is with a 50Mhz, so we are well within 
> the 10ns for the fastest read cycle.
> 
> I've run many experiments, and they all agree, only the lower byte lag 
> behind.  AFAICT, I've correctly disabled the flash RAM and the Ethernet. 
>  I'm at a loss.
> 

This is with what board, the Cyclone board?

I've run the SRAM with a 100 MHz clock on the Cyclone board as part of 
my ABC80 design without any timing problems, although I believe I'm 
giving it two clock cycles.

My guess would be that you're violating a setup time somewhere, and that 
one of the chips on your board is slightly slower than the others. 
Without the data sheets in front of me I'm not sure exactly what the 
setup requirements are.

	-hpa