[Lancelot] Slow lower order byte on fse_d?

Tommy Thorn tommy at numba-tu.com
Mon Aug 8 17:47:48 PDT 2005

H. Peter Anvin said:
> This is with what board, the Cyclone board?


> I've run the SRAM with a 100 MHz clock on the Cyclone board as part of
> my ABC80 design without any timing problems, although I believe I'm
> giving it two clock cycles.

That would be a good test.  How much do I need to change to get your ABC80 to
use a 100 MHz clock?  Either I'm doing something wrong (which I hope) or your
ABC80 shouldn't be able to run at 100 MHz either.

> My guess would be that you're violating a setup time somewhere,

Well, all internal FPGA timing constraints are ok and as all inputs and
outputs are buffered the situation for read is really simple: tAC is 10ns plus
whatever is needed for the PCB trace and the IOB.  Definitely much less then

> and that
> one of the chips on your board is slightly slower than the others.

Only, there are two chips, each providing 16-bits, but I only see this on 8 of
them.  The fact that the 24 bits that doesn't go to the flash ram works as
expected is too much of a coincidence.

Only explanation I can see is either
- the flash RAM isn't disabled correctly or
- the flash RAM is damaged.


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