[Lancelot] Slow lower order byte on fse_d?

[H. Peter Anvin]

Tommy Thorn wrote:
> H. Peter Anvin said:
> 
>>This is with what board, the Cyclone board?
> 
> Yes.
> 
>>I've run the SRAM with a 100 MHz clock on the Cyclone board as part of
>>my ABC80 design without any timing problems, although I believe I'm
>>giving it two clock cycles.
> 
> That would be a good test.  How much do I need to change to get your ABC80 to
> use a 100 MHz clock?  Either I'm doing something wrong (which I hope) or your
> ABC80 shouldn't be able to run at 100 MHz either.
> 

The CPU uses cpu_clk (25 MHz) in the ABC80 design, but the MMU and the 
SRAM controller uses fast_clk, which is 100 MHz.

> 
> Only, there are two chips, each providing 16-bits, but I only see this on 8 of
> them.  The fact that the 24 bits that doesn't go to the flash ram works as
> expected is too much of a coincidence.
> 
> Only explanation I can see is either
> - the flash RAM isn't disabled correctly or
> - the flash RAM is damaged.
> 

All I do in ABC80 is:

    assign flash_cs_n = 1;       // Disable flash ROM
    assign sram_cs_n  = 0;       // Enable SRAM
    assign enet_aen   = 0;       // Enable Ethernet

	-hpa